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19-2342; Rev 0; 02/02
KIT EVALUATION AVAILABLE
2.7Gbps Post Amp with Automatic Gain Control
General Description
The MAX3861 is a low-power amplifier with automatic gain control (AGC), designed for WDM transmission systems employing optical amplifiers and requiring a vertical threshold adjustment after the post amp. Operating from a single 3.3V supply, this AGC amplifier linearly amplifies/attenuates the input signal while maintaining a fixed output-voltage swing at data rates up to 2.7Gbps. Both the input and output are on-chip terminated to match 50 interfaces. This amplifier has a small-signal bandwidth of 3.4GHz and an input-referred noise of 0.26mVRMS. Over an input signal range of 6mVP-P to 1200mVP-P (46dB), the MAX3861 delivers a constant output amplitude that is adjustable from 400mVP-P to 920mVP-P. Variation in output swing is controlled within 0.2dB over a 16dB input range. The MAX3861 provides a received-signalstrength indicator (RSSI) that is linear, within 2.5%, for input signal levels up to 100mVP-P and an input signal detect (SD) with programmable threshold. o Single 3.3V Power Supply o 72mA Supply Current o 3.4GHz Small-Signal Bandwidth o 0.26mVRMS Input-Referred Noise o 6mVP-P to 1200mVP-P Input Range (46dB) o Input Signal Detect with Programmable Threshold o RSSI (Linear Up to 100mVP-P) o Adjustable Output Amplitude o 0.2dB Output Voltage Variation (Over 16dB Input Signal Variation)
Features
MAX3861
Applications
OC-48/STM-16 Transmission Systems WDM Optical Receivers Long Reach Optical Receivers Continuous Rate Receivers
PART MAX3861EGG MAX3861E/D
Ordering Information
TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 24 QFN* Dice**
Typical Application Circuit
CCD 0.1F
*EP = Exposed Pad **Dice are designed to operate over a -40C to +120C junction temperature (TJ) range, but are tested and guaranteed at TA = +25C.
Pin Configuration
GND CZ+ CZCD20 TOP VIEW CD+ RSSI 19 18 17 16 SD VCC OUT+ OUTVCC OSM 15 14 13 7 VREF 8 SC 9 GND 10 CG+ 11 CG12 GND
CCZ 0.22F MAXIM 2.7Gbps TIA 50 0.1F 50 0.1F
CZ+ CZIN+
CD+
CD-
CG+ CGOUT+
CCG 2200pF
24 TH 1 2 3 4 5 6
23
22
21
50
IN-
MAX3861
OUT-
50
MAXIM MAX3873 CDR
VCC IN+ IN-
MAX3861
TH RTH 1.8k SD RSSI RRSSI 50k EN
OSM VREF SC ROSM 50k
VCC EN
CONTROLLED IMPEDANCE LINE
QFN-EP
________________________________________________________________ Maxim Integrated Products
1
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2.7Gbps Post Amp with Automatic Gain Control MAX3861
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ......................................................-0.5V to +4.0V Voltage at IN+, IN- ..........................(VCC - 1.5V) to (VCC + 0.5V) Voltage at CZ+, CZ-, CG+, CG-, CD+, CD- ............................(VCC - 3.5V) to (VCC + 0.5V) Voltage at SC, SD, EN, TH, OSM, VREF, and RSSI............................-0.5V to (VCC + 0.5V) CML Input Current at IN+, IN-.............................................25mA CML Output Current at OUT+, OUT- ..................................25mA Storage Temperature Range .............................-55C to +150C Operating Junction Temperature Range ...........-55C to +150C Lead Temperature (soldering, 10s) .................................+300C Processing Temperature (Die).........................................+400C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = -40C to +85C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS RSSI and SD enabled (Notes 2, 3) Supply Current ICC RSSI and SD disabled (Notes 2, 3) VNOISE = 100mVP-P, fNOISE 10MHz, VSC = 2V (Note 4) Single ended to VCC 2.7GHz 2.7GHz to 4.0GHz VCC 0.3 Up to 6GHz at max gain, CCZ = 0.1F VIN Differential 0.9 linearity 1.1 ROUT Single ended to VCC 2.7GHz 2.7GHz to 4.0GHz VSC = 0 Output Common-Mode Level RL = 50 to VCC VSC = 2V VSC = 0, RL = 50 to VCC (Note 5) Maximum Differential Output Offset VSC = 2V, RL = 50 to VCC (Note 5) 6mVP-P VIN 700mVP-P 700mVP-P VIN 1200mVP-P 6mVP-P VIN 700mVP-P 700mVP-P VIN 1200mVP-P VSC = 0 VSC = 2V 40 6 700 650 50 16 11 VCC 0.13 VCC 0.28 3 8 mV 5.5 11 28 14 V 60 0.26 At minimum gain At maximum gain At minimum gain At maximum gain VIN = 1000mVP-P VIN = 10mVP-P MIN TYP 72 94 57 78 35 dB 25 2.7 RIN 40 50 21 15 VCC 0.35 1200 60 Gbps dB V mVRMS mVP-P mVP-P dB MAX 86 112 69 94 mA UNITS
Power-Supply Noise Rejection Input Data Rate Input Resistance Input Return Loss Input Common-Mode Level Input-Referred Noise Input Voltage Range Maximum Differential Input Voltage for Linear Operation Output Resistance Output Return Loss
PSNR
2
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2.7Gbps Post Amp with Automatic Gain Control
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = -40C to +85C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER Differential Output Amplitude Output Amplitude Variation Small Signal Bandwidth Low-Frequency Cutoff Deterministic Jitter Output Signal Monitor Voltage Output Signal Monitor Linearity SC Input Range AGC Loop Constant VOSM SYMBOL VOUT VOUT BW CONDITIONS RL = 50 to VCC (Note 6) VSC = 0 VSC = 2V At minimum gain At maximum gain MIN 300 760 2.5 2.2 TYP 400 920 0.2 3.4 2.9 7.6 15 VOUT = 920mVP-P VOUT = 400mVP-P 0 16 55 mV VIN = 100mVP-P 1800 2.5 2.5 100 10 CG+ and CG- are open (Note 11) (Note 12) 10mVP-P VIN 100mVP-P 2mVP-P VIN 10mVP-P (Note 13) Sourcing 20A current Sinking 2mA current VIL VIH IIL IIH VIL = 0 VIH = 2.0V RVREF 40k 2.0 2.0 10 10 2.4 0.44 0.8 2.8 10 70 44 10 4.5 4.5 6.3 12 8 2 % mVP-P mVP-P s s % dB V V V V A A V 2.0 0.9 10 2.0 V % V s MAX 500 1050 1.0 5.5 4.3 13 50 UNITS mVP-P dB GHz kHz psP-P
MAX3861
VIN 6mVP-P, RL = 50 to VCC (Notes 6, 7) (Note 3) CCZ = 0.1F (Note 8) ROSM 2k (Note 6) 0V VSC 2V (Note 6) (Note 9) Without external capacitor CCG, VSC = 0 (Note 10)
RSSI Output Voltage
RSSI
RRSSI 2k, VSC = 0 (Note 6) 6mVP-P VIN 100mVP-P
VIN = 2mVP-P
RSSI Linearity Minimum SD Assert Input Maximum SD Assert Input SD Assert Time SD Deassert Time SD Accuracy SD Hysteresis SD Output High Voltage SD Output Low Voltage EN Input Low Voltage EN Input High Voltage EN Input Low Current EN Input High Current VREF Output Voltage
2mVP-P VIN 100mVP-P (Note 14)
Note 1:
Note 2: Note 3: Note 4:
Electrical characteristics are measured or characterized using a 223 - 1PRBS at 2.7Gbps with input edge speeds 200ps, unless otherwise noted. Dice are tested at TA = +25C only. All AC specifications are guaranteed by design and characterization, unless otherwise noted. Supply current measurement is taken with AC-coupled inputs and excludes output currents into 50 loads. Minimum gain is defined as VIN = 1200mVP-P and VOUT = 400mVP-P. Maximum gain is defined as VIN = 6mVP-P and VOUT = 920mVP-P. Reference gain is measured at 100MHz. Power-supply noise rejection is characterized with a 2.7Gbps 1100 pattern on the input. It is calculated by the equation PSNR = 20log(VCC / (VOUT)), where VOUT is the change in differential output voltage because of power-supply noise. See Power Supply Noise Rejection vs. Frequency in the Typical Operating Characteristics. _______________________________________________________________________________________ 3
2.7Gbps Post Amp with Automatic Gain Control MAX3861
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = -40C to +85C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.) (Note 1) Note 5: Note 6: Note 7: Note 8: See Distribution of Differential Output Offset (Worst-Case Conditions) in the Typical Operating Characteristics. Characterized with a 675Mbps 1-0 pattern. Measurements are taken over an input signal range of 16dB. Deterministic jitter is defined as the arithmetic sum of PWD (pulse-width distortion) and PDJ (pattern-dependent jitter). Deterministic jitter is the difference of total jitter and random jitter, with system jitter calibrated out. It is measured with a 27 - 1PRBS, and 80CIDs with DC-coupled outputs. Typical input resistance of SC pin is 40k. AGC loop time constant is measured with a 20dB change in the input and VSC held constant. With an external capacitor CCG of 0.022F connected between CG+ and CG-, a typical AGC loop time constant of 760s is achieved. SD deassert time depends on the AGC loop time constant set by CCG. SD accuracy is defined as the part-to-part variation of the SD threshold at a fixed RTH value. See Distribution of SD Hysteresis (Worst-Case Conditions) in the Typical Operating Characteristics. Measurements are taken over an input signal range of 20dB.
Note 9: Note 10: Note 11: Note 12: Note 13: Note 14:
Typical Operating Characteristics
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
OUTPUT AMPLITUDE vs. INPUT AMPLITUDE
MAX3861 toc01
DISTRIBUTION OF SD HYSTERESIS (WORST-CASE CONDITIONS)
MAX3861 toc02
DETERMINISTIC JITTER VS. INPUT AMPLITUDE
18 DETERMINISTIC JITTER (psP-P) 16 14 12 10 8 6 4 2
MAX3861 toc03
1000 900 OUTPUT AMPLITUDE (mVP-P) 800 700 600 500 400 300 200 100 0 200 400 600 800 1000 223 - 1PRBS AT 2.7Gbps VSC = GND VSC = 2.0V
25 VCC = 3.0V VSC = 2.0V VIN = 2mVP-P TA = -40C MEAN = 4.52dB = 0.79dB
20
20 PERCENT OF UNITS (%)
15
10
5
0 1200 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 SD HYSTERESIS (dB) INPUT AMPLITUDE (mVP-P)
0 1 10 100 1000 10,000 INPUT AMPLITUDE (mVP-P)
SUPPLY CURRENT vs. TEMPERATURE
MAX3861 toc04
EYE DIAGRAM, MINIMUM INPUT
MAX3861 toc05
EYE DIAGRAM, MAXIMUM INPUT
MAX3861 toc06
100 95 90 SUPPLY CURRENT (mA) 85 80 75 70 65 60 55 50 -40 -10 20 50 80 EN = GND EN = VCC EXCLUDES OUTPUT LOAD CURRENTS VIN = 1200mVP-P VSC = 0
VIN = 6mVP-P 223 - 1 PRBS
VIN = 1200mVP-P 223 - 1 PRBS
76ps/div
76ps/div
TEMPERATURE (C)
4
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2.7Gbps Post Amp with Automatic Gain Control
Typical Operating Characteristics (continued)
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
POWER-SUPPLY NOISE REJECTION vs. FREQUENCY
POWER-SUPPLY NOISE REJECTION (dB)
MAX3861 toc07
MAX3861
|S22| vs. FREQUENCY
-5 -10 |S22| (dB) -15 -20 -25
MAX3861 toc08
SIGNAL DETECT THRESHOLD vs. RTH
MAX3861 toc09
80 70 60 50 40 30 20 10 0 5k 10k 100k FREQUENCY (Hz) 1M VIN = 10mVP-P VIN = 1000mVP-P
0
100 SD ASSERT THRESHOLD (mVP-P)
10
-30 -35 -40 10M 50M 100M 1G FREQUENCY (Hz) 10G MEASURED ON EVALUATION BOARD
1 100 1000 RTH () 10,000 100,000
|S11| vs. FREQUENCY
MAX3861 toc10
OUTPUT SIGNAL AMPLITUDE vs. SC PIN VOLTAGE (VIN = 1.0VP-P)
MAX3861 toc11
RSSI OUTPUT vs. INPUT AMPLITUDE
MAX3861 toc12
0 -5 -10 |S11| (dB) -15 -20 -25 -30 -35 -40 50M 100M 1G FREQUENCY (Hz) MEASURED ON EVALUATION BOARD
1000 900 800 700 600 500 400
3.5 3.0 RSSI OUTPUT (V) 2.5 2.0 1.5 1.0 0.5 0 223 - 1PRBS
VOUT (mVP-P)
10G
0
0.5
1.0 VSC (V)
1.5
2.0
0
50
100
150
200
250
300
INPUT AMPLITUDE (mVP-P)
DISTRIBUTION OF DIFFERENTIAL OUTPUT OFFSET (VSS = 0V)
MAX3861 toctoc13
DISTRIBUTION OF DIFFERENTIAL OUTPUT OFFSET (VSC = 2V)
9 8 PERCENT OF UNITS (%) 7 6 5 4 3 2 1 VCC = 3.6V VSC = 2.0V VIN = 700mVP-P TA = -40C
MAX3861 toc14
25 VCC = 3.6V VSC = 0V VIN = 700mVP-P TA = -40C
10
20 PERCENT OF UNITS (%)
15
10
5
0 -10 -8 -6 -4 -2 0 2 4 6 8 10 DIFFERENTIAL OUTPUT OFFSET (mV)
0 -16 -12 -8 -4 0 4 8 12 16 DIFFERENTIAL OUTPUT OFFSET (mV)
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2.7Gbps Post Amp with Automatic Gain Control MAX3861
Pin Description
PIN 1 2, 5, 14, 17 3 4 6 7 8 9, 12, 22 10 11 13 15 16 18 19 NAME TH VCC IN+ INEN VREF SC GND CG+ CGOSM OUTOUT+ SD RSSI FUNCTION Input Signal Detect Threshold Programming Pin. Attach a resistor between this pin and ground to program the input signal detect assert threshold. Leaving this pin open sets the signal detect threshold to its absolute minimum value (<2mVP-P). See the Design Procedure section. Supply Voltage Connection. Connect all VCC pins to the board VCC plane. Positive CML Signal Input with On-Chip Termination Resistor Negative CML Signal Input with On-Chip Termination Resistor Signal Detect Enable. Set high (2.0V) or leave open to enable the input signal detection (RSSI and SD) circuitry. Set low (0.4V) to power-down the input signal detection circuitry. Reference Voltage Output (2.0V). Connect this pin to the SC pin for maximum output signal swing. Output Amplitude External Control. Ground SC for minimum output amplitude. Apply 2.0V to SC or connect SC directly to VREF for maximum output amplitude. Ground. Connect all GND pins to the board ground plane. Connection for AGC Loop Capacitor. A capacitor connected between CG+ and CG- sets the AGC loop time constant. Connection for AGC Loop Capacitor. A capacitor connected between CG+ and CG- sets the AGC loop time constant. Output Signal Monitor. This DC signal is linearly proportional to the output signal amplitude. Negative CML Data Output with On-Chip Back-Termination Resistor Positive CML Data Output with On-Chip Back-Termination Resistor Input Signal Detect. Asserts logic low when the input signal level drops below the programmed threshold. Received Signal Strength Indicator. Outputs a DC signal that is linearly proportional to the input signal amplitude. Connection for Signal Detect Capacitor. A capacitor connected between CD+ and CD- sets the offset-cancellation loop time constant of the input signal detection. See the Detailed Description section. Connection for Signal Detect Capacitor. A capacitor connected between CD+ and CD- sets the offset-cancellation loop time constant of the input signal detection. See the Detailed Description section. Connection for Offset-Cancellation Loop Capacitor. A capacitor connected between CZ+ and CZsets the offset-cancellation loop time constant of the main signal path. See the Detailed Description section. Connection for Offset-Cancellation Loop Capacitor. A capacitor connected between CZ+ and CZsets the offset-cancellation loop time constant of the main signal path. See the Detailed Description section. Maxim recommends connecting the exposed pad to board ground.
20
CD-
21
CD+
23
CZ-
24 EP
CZ+ Exposed Pad
6
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2.7Gbps Post Amp with Automatic Gain Control
Detailed Description
Figure 1 is a functional diagram of the MAX3861 automatic gain-control amplifier. The MAX3861 is divided into three sections: main signal path, input signal detection, and output signal detection.
IN+ VCC CZ+ CZ-
MAX3861
OUT+ MAIN SIGNAL PATH
Main Signal Path
The main signal path consists of variable gain amplifiers with CML output levels and an offset cancellation loop. This configuration allows for overall gains ranging from -9.5dB to 43.5dB.
IN-
OUTOSM INPUT SIGNAL DETECT CONTROL BLOCK AND OUTPUT SIGNAL DETECT SC VREF CG+ CG-
Offset-Cancellation Loop
The offset-cancellation loop partially reduces additional offset at the input. In communications systems using NRZ data with a 50% duty cycle, pulse-width distortion present in the signal or generated by the transimpedance amplifier appears as input offset and is partially removed by the offset cancellation loop. An external capacitor is required between CZ+ and CZ- to compensate the offset cancellation loop and determine the lower 3dB frequency of the signal path.
CD+ CDRSSI
MAX3861
SD CIRCUITRY
SD
EN
TH RTH GND
Input Signal Detection and SD Circuitry
The input signal detection circuitry consists of variable gain amplifiers and threshold voltages. Input signal detection information is compared to an internal reference and creates the RSSI voltage and an internal reference signal. The signal detect (SD) circuitry indicates when the input signal is below the programmed threshold by comparing a voltage proportional to the RSSI signal with internally generated control voltages. The SD threshold is set by a control voltage developed across the external TH resistor (RTH). Two control voltages, V ASSERT and V DEASSERT , define the signal detect assert and deassert levels. To prevent SD chatter in the region of the programmed threshold, 2.8dB to 6.3dB of hysteresis is built into the SD assert/deassert function and thus, once asserted, SD is not deasserted until sufficient gain is retained. When input signal detection (SD and RSSI) is not required, tie EN to a TTL low to power-down this circuitry.
Figure 1. Functional Diagram
Output Signal Monitor and Amplitude Control
Output amplitude typically can be adjusted from 400mVP-P to 920mVP-P by applying a control voltage (0V to 2.0V) to the SC pin. See Output Signal Amplitude vs. SC Pin Voltage in the Typical Operating Characteristics. Connect the VREF pin (2.0V) to the SC pin for maximum output amplitude. The output signal monitor pin provides a DC voltage that is linearly proportional to the output signal.
Design Procedure
Program the SD Threshold
The SD threshold is programmed by an external resistor, RTH, between the range of 2mVP-P to 100mVP-P. The circuit is designed to have approximately 4.5dB of hysteresis over the full range. See Signal Detect Threshold vs. R TH graph in the Typical Operating Characteristics for proper sizing.
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7
2.7Gbps Post Amp with Automatic Gain Control MAX3861
Select the Coupling Capacitors
When AC-coupling is desired, coupling capacitors CIN and COUT should be selected to minimize the receiver's deterministic jitter. Jitter is decreased as the input low-frequency cutoff (fIN) is decreased. fIN =
Setting the Automatic Gain-Control Loop Time Constant (Selecting CCG)
The automatic gain-control loop time constant is determined by the external capacitor connected between CG+ and CG-. A value of at least 0.0022F is recommended
[
1
2(50)(CIN )
]
Programming the Output Amplitude (Programming the SC Pin)
Output amplitude can be programmed from 400mVP-P to 920mVP-P by applying a voltage to the SC pin. See Output Signal Amplitude vs SC Pin Voltage in the Typical Operating Characteristics.
For ATM/SONET or other applications using scrambled NRZ data, select (CIN, COUT) 0.1F, which provides fIN < 32kHz. For Fibre Channel, Gigabit Ethernet, or other applications using 8B/10B data coding, select (CIN, COUT) 0.01F, which provides fIN <320kHz.
Applications Information
Wire Bonding Die
For high current density and reliable operation, the MAX3861 uses gold metallization. Make connections to the dice with gold wire only, and use ball-bonding techniques (wedge bonding is not recommended). The MAX3861 has two types of bond pads: the dimensions for square bondpads are 94.4 microns by 94.4 microns; the dimensions for the octagonal bondpads are 33.6 microns per side. Die thickness is 12mils (0.305mm).
Setting the Offset-Cancellation Loop Time Constant for Input Signal Detection Circuitry (Selecting CCD)
The capacitor between CD+ and CD- determines the time constant of the input signal detection DC offsetcancellation loop. A value of 0.1F for CCD provides a low-frequency cutoff (fC) below 10kHz. If a lower cutoff frequency is desired, 0.22F gives fC = 4.5kHz and 0.47F gives fC = 2.1kHz. To guarantee stable operation, a capacitor of less than 0.01F should not be used.
Setting the Offset-Cancellation Loop Time Constant for the Main Signal Path (Selecting CCZ)
The capacitor between CZ+ and CZ- determines the time constant of the signal path DC offset-cancellation loop. To maintain stability, it is important to keep a onedecade separation between fIN and the low-frequency cutoff (fOC) associated with the DC offset-cancellation circuit. For SONET applications, f IN < 32kHz, so f OCMAX < 3.2kHz. Therefore, C CZ = 0.22F (f OC = 2.99kHz), CCZ = 0.47F (fOC = 1.4kHz), or a greater value may be used.To guarantee stable operation, a capacitor of less than 0.01F should not be used.
8
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2.7Gbps Post Amp with Automatic Gain Control MAX3861
VCC
VCC
50
50
50 IN+
50
OUT+
OUT-
IN-
Figure 2. Input Interface
Figure 3. Output Interface
VCC
VCC
VCC CG+ TH 200
180k
RTH
200k
CG-
180k
Figure 4. TH Interface
Figure 5. CG Interface _______________________________________________________________________________________ 9
2.7Gbps Post Amp with Automatic Gain Control MAX3861
Pad Coordinates
VCC
PAD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26. 27 28 29 30 31 32
PAD NAME N.C. EN N.C. VCC ININ+ VCC TH GND CZ+ CZGND N.C. N.C. CD+ CDRSSI GND SD VCC OUT+ OUTVCC OSM GND N.C. CGCG+ GND SC N.C. VREF
COORDINATES (m) 47, 47 44, 264 44, 419 47, 582 43, 776 43, 927 45, 1123 44, 1452 47, 1672 306, 1672 432, 1672 593, 1671 908, 1672 1034, 1672 1181, 1672 1307, 1672 1461, 1672 1662, 1671 1669,1458 1668, 1126 1671, 927 1671, 776 1668, 577 1669, 272 1661, 47 1356, 47 1207, 45 1081, 45 670, 47 513, 45 355, 45 199, 45
56.2k CZ2k CZ+ 56.2k 2k VCC 56.2k CD2k CD+ 56.2k 2k
Figure 6. CD Interface
Coordinates are for the center of the pad. Coordinate 0, 0 is the lower left corner of the passivation opening for pad 1.
Figure 7. CZ Interface
10
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2.7Gbps Post Amp with Automatic Gain Control
Chip Topography
CZ(PAD 11) CZ+ (PAD 10) GND (PAD 12) N.C. (PAD 13) CD+ (PAD 15) RSSI (PAD 17)
MAX3861
N.C. (PAD 14)
CD(PAD 16)
GND (PAD 9) TH (PAD 8)
GND (PAD 18) SD (PAD 19)
VCC (PAD 7) IN+ (PAD 6) IN(PAD 5) VCC (PAD 4) N.C. (PAD 3) EN (PAD 2) N.C. (PAD 1)
VCC (PAD 20) OUT+ (PAD 21) OUT(PAD 22) VCC (PAD 23)
0.081" (2.06mm)
OSM (PAD 24)
VREF (PAD 32) N.C. (PAD 31)
SC (PAD 30) GND (PAD 29) 0.081" (2.06mm)
CG+ (PAD 28)
N.C. (PAD 26)
GND (PAD 25)
CG(PAD 27)
TRANSISTOR COUNT: 952 Insulated SiGe Bipolar PROCESS: Bipolar F60 DIE SIZE: 2.06mm 2.06mm
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11
2.7Gbps Post Amp with Automatic Gain Control MAX3861
Package Information
12,16,20, 24L QFN.EPS
12
______________________________________________________________________________________
2.7Gbps Post Amp with Automatic Gain Control
Package Information (continued)
MAX3861
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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